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Memory Mask Design Engineer at NVIDIA — Bengaluru

Experience2+ yrs
SalaryNot disclosed
Work modeunknown
Leveljunior
Posted18 Sept 2026

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About NVIDIA

NVIDIA is hiring in Bengaluru in semiconductors electronics. This role looks for around 2+ years of experience.

The role

A junior Memory Mask Design Engineer role at NVIDIA (semiconductor manufacturing) where you implement IC layout for high-performance high-speed CMOS digital memory in advanced foundry CMOS process nodes (3nm, 5nm, 7nm and lower), including full custom memory layout delivery and adopting best layout practices. You will use Cadence EDA tools and apply memory layout knowledge such as bitcells, Decoder, LIO, EM/IR quality checks, LOD, Dummification, fills, along with floor planning, block-level routing and macro-level assembly. Location is Bengaluru, Karnataka, India (work mode not stated).

Full job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for a Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.

What You'll Be Doing

Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.IP layout will comprise of significant digital components.Adopting and putting in place the best layout practices/methodology for composing digital Memory layoutsFollow company procedures and practices for IC layout activities.

What We Need To See

B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ Years of proven experience in Memory layout in advanced CMOS process.Detailed knowledge of industry standard EDA tools for Cadence.Experience with layout of high-performance memories of various types.Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)Experience with floor planning, block level routing and macro level assembly.Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

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