Low Power Design Engineer(NPU)-Sr Lead

Qualcomm · Bengaluru

  • Experience3+ yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Levelmid
  • Posted1 Oct 2026

About Qualcomm

Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 3+ years of experience.

Skills

  • Unified Power Format
  • Common Low Power
  • PrimeTime PX
  • Tcl
  • Perl
  • RTL design
  • power analysis
  • synthesis
  • physical implementation
  • DSP

The role

A low power design engineer at a semiconductor technology company develops power intent for DSP IP using Unified Power Format, validates it with Common Low Power, and analyzes dynamic and leakage power with PrimeTime PX, while applying Tcl automation and Perl.

Full job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Hands on experience in writing UPF based on power spec for block/SOC having complex power crossingsHands on experience in validating power intent using CLPHands on experience on Power analysis using PTPX Understanding on issues related to MV cell (isolation, level shifter, retention etc) insertion during synthesisGood understanding on optimization of dynamic & leakage power during RTL development and physical implementationGood understanding on power correlation between Pre-Si and Post-SiAutomation skill in TCL and/or PerlGood communication skill

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Additional Job Description

Creating power spec for Qualcomm DSP IPs based on the design specPower intent development using UPF for DSP IPs based on power specPower intent validation at RTL level , Gate level (synthesis , PD ) using CLPFixing power intent based on PA DV feedback for any issue related to power intent Debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly Dynamic and Leakage power projection of DSP IPs during starting of the projectDynamic and Leakage power no. generation using PTPX and tracking the same at different stages of implementation flowHighlighting issues related to dynamic and leakage power mismatch compared to the target and working with Synthesis and PD teams to fix the issuesWorking with cross function teams (SOC, Sub System etc) for smooth handoff of power intent and Dynamic & leakage power no. at different stages of project execution

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