Leader, ASIC Engineering | RTL, Datapath, Network Processing Unit

Job Summary

Meet the Team

Come join us and be part of the Cisco SiliconOne team and take part in crafting Ciscos groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact

Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

Leads ASIC engineering teams to deliver high-performance, power-efficient, and reliable ASICs for Ciscos diverse product platforms.

Leads teams in defining, designing, and verifying ASICs and ASIC subsystems to ensure alignment with stringent power, performance, and area (PPA) goals for deployment across Cisco s platforms.

Drives collaboration cross-functionally to achieve high-volume production with uncompromised quality.

Defines processes, methodologies, and tools for the design and implementation of complex ASIC developments, ensuring scalability, efficiency, and innovation.

Oversees the documentation, development, and validation of ASIC subsystems, ensuring robust designs that meet the demanding requirements of Ciscos product ecosystem.

Drives all aspects of implementation: Specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.

Review complex designs and makes recommendations for improvements.

Act as the design leader, owning and leading all the above aspects, including driving the technical decisions made at the program level with rest of the design teams, conducting weekly design meetings, sync-ups with stake holders and cross functional teams like Architecture, DV, PD, Emulation, SW, PSV and Silicon Operations.

Drives design solutions across the business. Ensure culture of code reviews and postmortems.

Minimum Qualifications

BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC.

Have led a design team for a minimum of 4 years

Architecture and implementation specification creation.

RTL development (Verilog, System Verilog, VCS, Spyglass, CDC, Formal verification)

Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.

Gate-level understanding of RTL and Synthesis

Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

Worked in design and execution management of high-scale, high-performance ASICs.

Planning overall design execution strategy and defining the requirements.

Conducting leading various architecture reviews.

Driving complex debugs and system level integration aspects

Valid experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.

Mentoring the senior resources in the team on architectural and design strategies.

Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.

Excellent communication skills both verbal and written

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