Lead Standard cell design/characterization Engineer
NXP Semiconductors · Bengaluru
- Experience7–9 yrs
- SalaryNot disclosed
- Work modeunknown
- Levellead
- Posted11 Sept 2026
About NXP Semiconductors
NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 7+ years of experience.
The role
Lead Standard cell circuit design/characterization engineer for NXP Semiconductors, working on standard cell library solutions including characterization, layout design and EDA development across RTL2GDS flows. You will perform circuit and MC simulations, handle Layout Dependent Effects, and develop EDA views such as Characterization of NLDM, CCSP, CCSN, and AOCV/LVF (including exposure to AOCV and LVF model characterization). Key tools and skills include Siemens, Cadence, and Synopsys EDA tools, plus MS Excel and PowerBI/Tableau, with added advantage for SKILL/Python/TCL/PERL scripting. Based in Bengaluru, Karnataka, India; work mode is not specified.
Full job description
Job Overview
NXP-CTO/DE/FDIP/Logic Library Team is responsible for all the standard Cell library solutions (Differentiated IP augmentation along with internalization for 3rd party library Ips). Consultancy to design teams on Reliability, DfT, Timing Closure, etc.
Job Qualification
Experience in Standard Cell Circuit design, Characterization and/or Layout design of various Standard cells and Macros (viz. flip flops, latches, multibit flip flops, level shifters, Power Switch Cells, Retention flops, Synchronizer cells etc.) in planer and non-planar technology nodes.At least 7-9 years of experience in StdCell domainAIML/Agentic AI literacyWork involved is Characterization, Layout design and EDA development of StdCells.Overview and good understanding of Circuit and MC simulations, Layout Dependent Effects and overall RTL2GDS flow (STA, PnR).Good understanding of CMOS and FinFET technologies.Good understanding and expertize in using of State-of-the-art EDA tools from Siemens, Cadence and Synopsys for simulations, characterization, and layout developments.Contribute in the improvement/development of circuit design, Characterization of StdCell libraries.Implement Innovative solutions within Standard cell library development domain.Develop EDA views including Characterization of NLDM, CCSP. CCSN and AOCV, LVF for standard cell librariesExposure to AOCV, LVF model characterization is plus.Working knowledge in MS Excel, PowerBI and/or Tableau could be an added advantage.Working Knowledge of SKILL / Python / TCL / PERL scripting could be an added advantage.
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