Lead RTL Engineer
Microsoft · Bengaluru
- Experience7–11 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelexecutive
- Posted2 Sept 2026
About Microsoft
Microsoft is hiring in Bengaluru in technology software. This role looks for around 7+ years of experience.
Skills
- SystemVerilog
- RTL Design
- Tapeout
- GDSII
- Synthesis
- Timing Closure
- Design Compiler
- Genus
- PrimeTime
- Tempus
- Processor Design
- DSP Design
- Datapath Design
- Advanced Process Nodes
- Code Review
The role
A design engineer at a semiconductor technology company develops SystemVerilog RTL for processor, DSP, and datapath-heavy designs, taking implementations through tapeout and GDSII while applying synthesis and timing closure. The role also uses Design Compiler, Genus, PrimeTime, and Tempus in physical design flows and guides hands-on code reviews.
Full job description
Requirements:
7+ years of RTL design experience in SystemVerilog.
At least 1 tapeout through to GDSII (not just RTL, you've seen the full flow).
Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or Tempus).
Processor, DSP, or datapath-heavy design experience.
Familiarity with advanced process nodes (28nm class or below).
Strong code review skills, you can spot timing hazards, FSM issues, and non-synthesizable patterns in review.
Comfortable leading a small team while remaining hands-on.