IP Verification Lead with PCIe

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

SMTS SILICON DESIGN ENGINEER

The Role

The focus of this role is to plan, build, and execute the verification plan for AMD's FPGA, ASIC IPs, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

Collaborate with architects, hardware engineers, and firmware engineers to understand product requirementsBuild test plan documentation for functionality, performance and product use caesDevelop UVM based testbench with support for directed and random test cases to achieve high quality designDebug test failures, drive bug finding and coverage convergence activitiesUse AI to drive efficiency and automationCollaborate with partner verification and validation teams to provide silicon debug support

PREFERRED EXPERIENCE:

Proficient in IP level ASIC verification.Knowledge of PCIe, CXL or other IO protocol requiredExperience with DMA verification is preferredProficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog   Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment.   Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language   Exposure to usage of LLMs, AI Agents in verification is preferredScripting language experience: Perl, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.