GPU STA/Timing Engineer (Senior Lead/Staff)

Qualcomm · Bengaluru

  • Experience6–10 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Posted23 Sept 2026
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About Qualcomm

Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 6+ years of experience.

Skills

  • static timing analysis
  • timing signoff
  • ASIC/SoC
  • SDC
  • MCMM/MMMC
  • timing closure
  • ECO implementation
  • SOCV/AOCV
  • signal integrity analysis
  • Synopsys PrimeTime
  • Physical Design
  • Tcl
  • Python

The role

A design verification engineer in a semiconductor product company develops ASIC/SoC timing signoff for high-performance GPU designs using static timing analysis, timing closure, and Synopsys PrimeTime. The role validates SDC constraints, performs MCMM/MMMC analysis, and applies Tcl/Python scripting to automate signoff flows.

Full job description

Job Summary

Qualcomm's GPU team is looking for experienced STA Engineers to drive timing signoff and closure for next-generation high-performance GPU designs. The role involves close collaboration with Architecture, RTL, Physical Design, DFT, and SoC teams to deliver best-in-class silicon products.

Responsibilities

Own block-level and full-chip STA signoff for GPU designs.

Develop and validate timing constraints (SDC).

Perform MCMM/MMMC timing analysis, timing closure, and ECO implementation.

Drive setup/hold, noise, SI, and low-power timing closure.

Collaborate with cross-functional teams to resolve timing issues.

Enhance STA methodologies, signoff flows, and automation.

Mentor junior engineers and provide technical leadership.

Required Qualifications

BS/MS in Electrical/Electronics Engineering or related field.

6-10 years of experience in ASIC/SoC STA and timing signoff.

Strong expertise in STA, MCMM/MMMC, SDC, timing closure, ECOs, SOCV/AOCV, and SI analysis.

Hands-on experience with Synopsys PrimeTime.

Strong understanding of Physical Design concepts and implementation flows.

Proficiency in Tcl/Python scripting.

Preferred Skills

Experience with GPU, CPU, AI/ML, or high-performance SoC designs.

Experience in advanced technology nodes (5nm and below).

Exposure to Fusion Compiler, ICC2, StarRC, Tempus, or Innovus.

Proven technical leadership and mentoring experience.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.