G7 Fellow – High-Speed Interfaces & Clocking Strategy

NXP Semiconductors · Bengaluru

  • Experience2–7 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Levelsenior
  • Posted17 Sept 2026
Apply for this job

About NXP Semiconductors

NXP Semiconductors is hiring in Bengaluru in semiconductors electronics. This role looks for around 2+ years of experience.

Skills

  • high-speed interfaces
  • clocking architectures
  • PLL technologies
  • technology roadmapping
  • portfolio analysis
  • make-or-buy strategy
  • clock generation
  • clock distribution
  • synchronization
  • timing integrity
  • PHY
  • SerDes
  • I3C
  • USB
  • eUSB
  • Ethernet
  • USXGMII
  • MIPI
  • DDR
  • PCIe
  • CXL
  • UCIe
  • chiplet interconnects
  • functional safety
  • benchmarking
  • architectural studies

The role

A semiconductor technology strategist at a product semiconductor company defines high-speed interface architectures and clocking roadmaps, shaping PLL technologies and chiplet interconnects for automotive, industrial, networking, and computing applications. The role evaluates SerDes, PHY, PCIe, and CXL technologies and guides make-or-buy decisions, architectural studies, and ecosystem standards engagement.

Full job description

Key Responsibilities

Technology Strategy & Roadmap Leadership

Define and drive NXP’s long-term strategy for high-speed interfaces, clocking architectures, PLL technologies, and associated analog foundation IP.Analyze current and future requirements across all NXP Business Lines and Product Lines.Develop technology roadmaps aligned with market trends, customer needs, and product strategies.Identify opportunities for technology consolidation, platform reuse, and architectural alignment across NXP.Establish strategic priorities and investment recommendations to strengthen NXP’s competitive position.

Portfolio Analysis & Make-or-Buy Decisions

Assess NXP’s portfolio requirements across automotive, industrial, secure connected edge, networking, and computing applications.Evaluate internal capabilities, external IP offerings, partnerships, and acquisition opportunities.Develop and recommend make-versus-buy strategies for PHYs, SerDes, clocking, PLL, and related technologies.Provide strategic guidance on technology investments based on technical differentiation, reuse potential, time-to-market, and business impact.

Clocking & PLL Technology Leadership

Define company-wide clocking and synchronization strategies.Drive the roadmap for next-generation clock generation and PLL solutions with focus on:Low jitterLow powerSmall areaScalability across process nodesHigh-performance operationFunctional safety requirementsLead development of architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.

High-Speed Interface Architecture

Provide technical leadership for connectivity technologies including:I3CUSB / eUSBEthernetUSXGMIIMIPIDDRPCIeCXLUCIeEmerging chiplet interconnect technologiesGuide future PHY and SerDes architectures supporting multi-gigabit and chiplet-based systems.

Innovation & Technical Excellence

Establish and maintain a long-term innovation roadmap for high-speed interfaces and clocking technologies.Anticipate emerging industry trends and identify opportunities for NXP differentiation.Drive benchmarking, technology assessments, and architectural studies.Foster technical excellence and innovation across engineering communities.Represent NXP in strategic technical discussions with customers, partners, standards bodies, and ecosystem leaders.

More information about NXP in India...