G7 Fellow – High-Speed Interfaces & Clocking Strategy

Nxp · Bengaluru

  • Experience7–20 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Levelexecutive
  • Posted17 Sept 2026
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About Nxp

Nxp is hiring in Bengaluru in semiconductors electronics. This role looks for around 7+ years of experience.

Skills

  • high-speed interfaces
  • clocking architectures
  • PLL technologies
  • analog foundation IP
  • technology roadmaps
  • portfolio analysis
  • make-versus-buy strategies
  • PHYs
  • SerDes
  • clock generation
  • clock distribution
  • synchronization
  • timing integrity
  • system-level clock management
  • I3C
  • USB
  • eUSB
  • Ethernet
  • USXGMII
  • MIPI
  • DDR
  • PCIe
  • CXL
  • UCIe
  • chiplet interconnect technologies

The role

A semiconductor technology strategist at a semiconductor electronics company defines high-speed interface and clocking roadmaps, architects PLL technologies, and evaluates SerDes architectures and chiplet interconnects. The role also guides technology investments and platform reuse across automotive, industrial, networking, and computing applications.

Full job description

Key Responsibilities

Technology Strategy & Roadmap Leadership

Define and drive NXP’s long-term strategy for high-speed interfaces, clocking architectures, PLL technologies, and associated analog foundation IP.

Analyze current and future requirements across all NXP Business Lines and Product Lines.

Develop technology roadmaps aligned with market trends, customer needs, and product strategies.

Identify opportunities for technology consolidation, platform reuse, and architectural alignment across NXP.

Establish strategic priorities and investment recommendations to strengthen NXP’s competitive position.

Portfolio Analysis & Make-or-Buy Decisions

Assess NXP’s portfolio requirements across automotive, industrial, secure connected edge, networking, and computing applications.

Evaluate internal capabilities, external IP offerings, partnerships, and acquisition opportunities.

Develop and recommend make-versus-buy strategies for PHYs, SerDes, clocking, PLL, and related technologies.

Provide strategic guidance on technology investments based on technical differentiation, reuse potential, time-to-market, and business impact.

Clocking & PLL Technology Leadership

Define company-wide clocking and synchronization strategies.

Drive the roadmap for next-generation clock generation and PLL solutions with focus on:

Low jitter

Low power

Small area

Scalability across process nodes

High-performance operation

Functional safety requirements

Lead development of architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.

High-Speed Interface Architecture

Provide technical leadership for connectivity technologies including:

I3C

USB / eUSB

Ethernet

USXGMII

MIPI

DDR

PCIe

CXL

UCIe

Emerging chiplet interconnect technologies

Guide future PHY and SerDes architectures supporting multi-gigabit and chiplet-based systems.

Innovation & Technical Excellence

Establish and maintain a long-term innovation roadmap for high-speed interfaces and clocking technologies.

Anticipate emerging industry trends and identify opportunities for NXP differentiation.

Drive benchmarking, technology assessments, and architectural studies.

Foster technical excellence and innovation across engineering communities.

Represent NXP in strategic technical discussions with customers, partners, standards bodies, and ecosystem leaders.

More information about NXP in India...

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