DSP/NSP Power Analysis & Correlation
Qualcomm · Bengaluru
- Experience5–6 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted25 Sept 2026
About Qualcomm
Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 5+ years of experience.
Skills
- pre-silicon power analysis
- silicon validation
- DSP architecture
- NSP architecture
- processor architecture
- SoC architecture
- power estimation
- power optimization
- performance characterization
- Python
- Shell
- Perl
- simulation
- emulation
- performance models
- power models
The role
A design verification engineer at a semiconductor company analyzes DSP and NSP architectures, performs pre-silicon power analysis and silicon correlation, and improves power estimation through Python automation and performance characterization. The role applies power modeling and workload characterization to identify optimization opportunities across architecture, RTL, and software layers.
Full job description
Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Systems Engineering
General Summary:
We are seeking a highly motivated Senior Engineer (5-6 years experience) to drive pre-si power analysis, optimization, and silicon correlation for next-generation DSP and NSP architectures. The role focuses on evaluating and improving pre-silicon power analysis methodologies, understanding the strengths and limitations of various power estimation tools, and enabling early power optimization through actionable insights.
The engineer will also work closely with silicon validation teams to characterize performance and power on silicon, compare results against pre-silicon estimates, and help improve correlation accuracy. This role requires a strong understanding of DSP/NSP architectures, workload behavior, packet/data flows, and the relationship between system activity, performance, and power consumption.
Key Responsibilities
Evaluate and compare pre-silicon power analysis and estimation tools across simulation, emulation, and modeling environments.
Analyze tool methodologies, identify gaps, and recommend enhancements to improve power estimation accuracy and usability.
Drive adoption of best-in-class capabilities from various power analysis tools to improve pre-silicon power optimization workflows.
Perform workload-level and block-level power analysis for DSP/NSP subsystems.
Identify power hotspots and optimization opportunities across architecture, RTL, and software layers.
Measure and characterize performance and power behavior on silicon platforms.
Correlate silicon measurements with pre-silicon estimates and investigate sources of mismatch.
Develop methodologies and automation to improve power prediction accuracy and correlation efficiency.
Analyze packet flows, data movement, memory traffic, and workload behavior to understand their impact on power and performance.
Collaborate with architecture, design, software, performance, and silicon validation teams to drive power-efficient solutions.
Generate technical reports and present findings to stakeholders and engineering leadership.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
5-6 years of experience in power analysis, performance characterization, silicon validation, architecture analysis, or related areas.
Strong understanding of processor and SoC architecture fundamentals.
Experience working with pre-silicon environments such as simulation, emulation, performance models, or power models.
Experience with silicon performance and power characterization.
Understanding of performance-per-watt tradeoffs and power optimization techniques.
Familiarity with scripting and automation using Python, Shell, Perl, or similar languages.
Strong analytical, debugging, and problem-solving skills.
Excellent communication and cross-functional collaboration abilities.
Preferred Qualifications
Experience with DSP, AI/ML accelerators, vector processors, or heterogeneous compute architectures.
Knowledge of power modeling, power estimation methodologies, activity-based analysis, and PMU-based profiling.
Understanding of packet/data flow analysis, memory hierarchy, bandwidth utilization, and workload characterization.
Experience correlating simulation, emulation, or modeling results against silicon measurements.
Experience working with large-scale performance and power datasets and visualization tools.
Desired Skills
Strong curiosity to explore new tools and methodologies.
Ability to translate complex power data into actionable optimization recommendations.
Passion for improving correlation between pre-silicon and post-silicon environments.
Self-driven mindset with strong ownership and execution capabilities.
Minimum Qualifications:
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.
OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.
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