DFT Engineer
Texas Instruments · Bengaluru
- Experience2–5 yrs
- SalaryNot disclosed
- Work modeonsite
- Levelmid
- Posted11 Sept 2026
About Texas Instruments
Texas Instruments is hiring in Bengaluru in semiconductors electronics. This role looks for around 2+ years of experience.
Skills
- DFT architecture
- scan insertion
- ATPG
- Memory BIST
- Gate-Level Simulation
- Tcl
- Perl
- Python
- scan compression
- IEEE 1149.1
- JTAG
- IEEE 1500
- low-power DFT
The role
A DFT engineer at a semiconductor product company develops scan insertion strategies and ATPG test patterns for automotive microcontrollers, designs Memory BIST solutions, and automates DFT flows with Tcl and Python. The role applies IEEE 1149.1 and IEEE 1500 standards to validate scan compression, low-power testing, and tape-out quality.
Full job description
Texas Instruments is hiring for the role DFT Engineer
Responsibilities of the candidate :
Develop and execute DFT architecture and scan insertion strategies for low cost MCUs
Implement and validate ATPG test patterns to achieve automotive grade fault coverage
Design and deploy Memory BIST (MBIST) solutions for embedded memories across SoC designs
Ensure DFT rule compliance throughout the design flow from RTL to tape-out
Debug and resolve complex ATPG, scan, and Gate-Level Simulation (GLS) violations
Perform DFT sign-off checks and ensure test coverage meets product quality targets
Develop and maintain Tcl, Perl, and Python scripts to automate DFT flows and improve efficiency
Continuously improve DFT methodologies, flows, and best practices within the team
Requirements :
Experience with scan compression techniques (e.g., Modus EDT/IJTAG)
Familiarity with IEEE 1149.1 (JTAG) / IEEE 1500 standards
Exposure to low-power DFT methodologies (clock gating, power domain testing)