DDR PHY Sr Staff Design Verification Engineer
Qualcomm · Bengaluru
- Experience12–15 yrs
- SalaryNot disclosed
- Work modeonsite
- Posted23 Sept 2026
About Qualcomm
Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 12+ years of experience.
Skills
- Functional Verification
- Verilog
- SystemVerilog
- UVM
- Formal Verification
- Coverage
- Gate Simulation (GLS)
- Low Power Verification
- Design Verification
- DDR-PHY architecture
- DFI protocol
- JEDEC standards
- IP-level verification
- Subsystem-level verification
The role
A design verification engineer in a semiconductor product company develops and validates DDR-PHY architectures using Functional Verification, Verilog, and SystemVerilog, closing coverage and debugging SoC issues. The role also applies UVM and Formal Verification to complex IP and subsystem designs.
Full job description
Job Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Experienced DDR-PHY Design Verification engineer to work on next generation System-on-chip (SoC) for smartphones, tablets, laptops.
Job Responsibilities
12 to 15 years of experience in Design Verification of complex IPs. Hands-on experience and very good understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.
Ownership of DV test bench and other associated collaterals (Checkers, Scoreboards, Assertion, Functional Coverage).
Develop test plan and test cases to cover design feature set, follow up with stake holders at different levels of test bench.
Work closely with Design, Subsystem/SOC, SVE teams on failure debugs, code/functional coverage closure, as well as DSF.
Debug of regression signatures and identifying bug fixes.
Responsible for Quality sign-off and required documentation.
Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams.
Expertise in IP level /Sub-system level verification.
Understanding of standard bus protocol like AHB, AXI protocols would be a plus.
Required Skillset
Experience in verification and general computational logic design/verification concepts.
Expertise in Verilog/System Verilog and UVM/OVM.
Functional Verification, Coverage, Gate Simulation (GLS), Low Power Verification, Formal Verification
Strong debugging, Analytical and problem-solving skills.
Experience in developing Monitors, Scoreboards, Sequencers that utilize System Verilog, and UVM methodologies for complex scenario generation and verification of DUT.
Experience in Scripting languages like Perl /Tcl would be a plus.
Post-si bring-up and HW-SW debug experience would be a plus.