CPU Physical Design Engineer
Qualcomm · Bengaluru
- Experience7–14 yrs
- SalaryNot disclosed
- RoleVLSI Engineer
- Work modeonsite
- Levelexecutive
- Posted14 Oct 2026
About Qualcomm
Qualcomm is hiring in Bengaluru in semiconductors electronics. This role looks for around 7+ years of experience.
Skills
- Physical Design
- timing signoff
- high frequency design convergence
- PPA
- PDN methodology
- RTL to GDSII
- STA
- Tcl
- Perl
- low power flow
The role
Physical design engineer at a semiconductor company. Implements high-speed cores from RTL to GDSII, leading Physical Design, static timing analysis, and power distribution network methodology while meeting power, performance, and area targets. Applies Tcl/Perl scripting and low power flow expertise.
Full job description
Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > Hardware Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
7-14 yrs experience in Physical Design and timing signoff for high speed cores.Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.Experience in leading block level or chip level Physical Design, STA and PDN activities.Work independently in the areas of RTL to GDSII implementation.Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.Strong problem-solving skills.
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