ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with experienced engineers across the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Engineer, Design Verification Responsibilities:

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goalsDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of hands-on experience in ASIC design verificationHands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodologyExperience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologiesExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications:

Experience with verification of ARM/RISC-V based sub-systems or SoCsTrack record of 'first-pass success' in ASIC development cyclesExperience with Design verification of Data-center applications like Video, AI/ML and Networking designsExperience with IP or integration verification of high-speed interfaces like PCIe, DDR, EthernetExperience with revision control systems like Mercurial(Hg), Git or SVNExperience in development of UVM based verification environments from scratchExperience working across and building relationships with cross-functional design, model and emulation teams

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.