Analog/Mixed Signal Pll Analog Designers

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Hardware Engineering

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Function

Qualcomm Mixed-Signal IP team is actively seeking analog circuit designers with 612 years of experience to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO/Data Converter IPs for SoCs and supporting their integration into Qualcomm's Mobile, Auto, IoT, and Compute products on leading-edge FinFET and advanced process nodes. Design goals include low-power and low-voltage analog designs for Qualcomm's low-power wireless products.

Responsibilities

Hands-on experience - Analog circuit design

Own the architecture, design, and development of analog and mixed-signal hard macros for the PLL IP design team.

Design multiple analog building blocks, including bias circuits, references, op-amps, LDOs, VCOs/DCOs, and high-speed custom digital blocks such as dividers and clock distribution.

Perform custom circuit design in the latest FinFET CMOS process technologies, deliver hard macros, and support customer integration and testing.

Set up, run, and analyze SPICE circuit simulations, and create behavioral models.

Collaborate closely with layout, digital design, physical design, and HSIO Bench/ATE teams.

Participate in internal customer requirement discussions to create clear design specifications.

Skills Experience

Minimum 6 years of transistor-level analog/mixed-signal design experience, preferably in PLL design, data converters (ADC/DAC), or other high-speed applications.

Experience using SPICE simulators, ADEXL, and Virtuoso.

Familiarity with custom analog layout, parasitic optimization, post-layout extraction, verification, and design review closure.

Understanding of signal integrity in high-speed wireline design is preferred.

Scripting experience to automate circuit design and verification workflows.

Ability to collaborate effectively with global cross-functional teams and communicate technical concepts clearly through documentation and presentations.

Preferred

Mixed-signal design experience, especially in PLL/DLL clocking architectures, high-speed interfaces, SoC integration, advanced CMOS/FinFET nodes, and scripting

Keywords

Analog Circuit Design

Mixed-Signal IP

PLL

DLL

LDO

Bias

Reference

VCO

DCO

Clock Distribution

ADC

DAC

SPICE

Virtuoso

ADEXL

FinFET

Analog Layout

Post-Layout Simulation