SoC Physical Design Engineer

Nokia · Ahmedabad

  • Experience8–9 yrs
  • SalaryNot disclosed
  • Work modeonsite
  • Levelexecutive
  • Posted16 Sept 2026
Apply for this job

About Nokia

Nokia is hiring in Ahmedabad in telecom. This role looks for around 8+ years of experience.

Skills

  • ASIC physical design flow
  • ASIC design methodologies
  • Fusion Compiler
  • Innovus
  • PrimeTime
  • TCL
  • Python
  • Perl
  • RTL-to-GDSII
  • Fixed-point modelling
  • Fixed-point performance verification
  • ASIC design
  • FPGA design
  • Hardware bring-up
  • Electrical Engineering
  • Electronics and Communication
  • VLSI
  • Microelectronics

The role

A physical design engineer at a telecommunications technology company implements optical network ASICs using ASIC physical design flow, EDA place-and-route tools, and timing analysis, while optimizing power, performance, and area. The role develops fixed-point models and supports RTL-to-GDSII implementation and hardware bring-up.

Full job description

Job Description

You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow , doing implementation to achieve best in class ASICs , which are optimized for power, performance and area metrics

How You Will Contribute And What You Will Learn

Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs Working as independent contributor in algorithm development, fixed-point modelling and fixed-point performance verification Working with experts of different areas to ensure the most competitive solutions Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues Supporting HW/SW bring-up and debug

Key Skills And Experience

8+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar Scripting experience in TCL, python or Perl Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics